When using a computer-aided design system to design microelectronic devices, a designer typically generates a behavioral description using a high-level description language or a circuit level description using a schematic capture tool. Thereafter, the designer can incrementally simulate and verify the design using logic level models incorporating accurate timing and delay information. At this stage, the design is represented as instances of logic cells having input and/or output ports. Furthermore, the circuit description includes structures called nets, which interconnect the ports on various logic cells. An active logic cell having at least one output port connected to the net is considered a driver cell. Tri-stated cells having at least one output port connected to the net or other cells having at least one input port connected to the net are considered load cells on the net.
When a designer simulates a circuit design, it is typically necessary to determine the logic delay associated with each driver cell. A logic delay is the period of time required for a signal transition at an input of a driver cell to be propagated to the output of the cell. For example, an input signal makes a transition from low to high, crossing a threshold voltage at time t.sub.0. This input transition may cause the signal at an output of the driver cell to transition, crossing a voltage threshold at time t.sub.1. The logic delay of the example cell is (t.sub.1- t.sub.0).
Previous methods for determining logic delay through a logic cell are disclosed in W. C. Elmore, The Transient Response of Damped Linear Networks with Particular Regard to Wide-Band Amplifiers, 19 Journal of Applied Physics 55 (1948), and L. T. Pillage and R. A. Rohrer, Asymptotic Waveform Analysis for Timing Analysis, CAD-6 IEEE Transactions on Computer Aided Design for Integrated Circuits, 352 (1990), which are herein incorporated by reference.
The total logic delay for each cell may be considered to be the sum of gate delay and interconnect delay components. The gate delay is influenced by many characteristics of the circuit, including the internal characteristics of the driver cell, the rise and fall times of the input signal, and the load capacitance presented by load cells connected to the net. The interconnect delay is influenced by the parasitic net impedance provided by the metal interconnect lines between the output port of the driver cell and the ports of the load cells. The net impedance may be considered to have two components: parasitic resistance and parasitic capacitance.
Before the circuit layout is performed, the actual interconnect lengths between circuit elements are not known. Therefore, estimates of parasitic resistance and capacitance may be used for logic delay calculations in the circuit. After layout, however, the actual physical layout (length) of each net is known, and a variety of improved approximations of interconnect resistance and capacitance (RC), obtained by parasitic RC extraction, may be employed in logic delay calculations. As device and interconnect geometries decrease, the influence of interconnect impedance on total logic delay increases. Therefore, the delay attributed to interconnect impedance may rival or exceed the delay attributed to the transistor behavior of the driver cell and the effect of the load capacitances presented by load cells on the net. The impact of interconnect delay is so significant that a dominance of interconnect delay over gate delay in deep submicron IC technology is widely asserted in the academic and electronic design automation (EDA) industry press. Accordingly, improvements in parasitic RC extraction can provide more accurate design simulations by improving overall logic delay accuracy.
Fast methods of parasitic impedance extraction are available from leading EDA vendors. For example, a Detailed Standard Parasitic Format (DSPF) file for a 240,000 gate design can be extracted in 14 minutes on a SPARC20 workstation using the AQUARIUS router from AVANT! CORPORATION. This fast method, however, uses simple resistance and capacitance models wherein the parasitic resistance and capacitance for each metal layer is assumed to be a constant value per unit length.
The actual capacitance effects of a length of interconnect are not constant per unit length, varying with metal line width, dielectric thickness and other fabrication and design characteristics. Therefore, the simple extraction method produces inaccurate results for a subset of nets within a design. Particularly, the complexity of multiple interconnect layers, combined with the proximity effects due to very narrow metal spacing, can induce an error of up to 50% using the simple capacitance model. Likewise, actual interconnect resistance is not constant per unit length, varying with sheet resistance and line width. Nevertheless, the simple models are accurate for a majority of nets in a design.
Modern EDA vendors also offer advanced parasitic RC extraction software that is more accurate than the simple RC model but which require significantly longer central processor unit (CPU) run times. For example, the STAR-R software from AVANT! CORPORATION uses a 4-step extraction process. First, a capacitance-only (C-only) extraction is performed on every net in the design. Second, only resistance is extracted on every net (R-only). Third, delay calculations are performed to compare the R-only delay to the C-only delay. The delay calculations consume a significant amount of CPU time. On a net-by-net basis, if the difference between the R-only delay and the C-only delay exceeds a certain error criteria, the net is identified for detailed parasitic RC extraction. Fourth, detailed extraction is performed on the identified nets using a distributed impedance model to address the complexity of the narrow metal spacing and other deep submicron effects.
This detailed parasitic RC extraction process incurs long CPU run times, resulting in unacceptably long layout cycle times. For the same 240,000 gate design mentioned above, the CPU run time required for STAR-R on a SPARC20 is several hours. It is desirable to minimize the CPU run time required for parasitic RC extraction while maintaining acceptable accuracy of parasitic results. CPU run time can be improved by using the highest performance CPU platform available, but the growth rate of IC design complexity is keeping pace with increases in CPU clock rates. In addition, the cost of capital to purchase or lease the highest performance engineering workstations is extremely high. Furthermore, more accurate and more complex parasitic resistance and capacitance models may be employed to increase the accuracy of detailed parasitic extraction, but these models also increase the required CPU run time.
Therefore, there exists a need to select nets for which the simple parasitic model is accurate, to select the interconnect nets for which a more detailed parasitic extraction is required, and to select nets where parasitic interconnect effects are negligible. Furthermore, this method of selection must minimize CPU run time requirements so as not to contribute significantly to the CPU run time requirements of the overall parasitic RC extraction process. Accordingly, there exists a need to alleviate CPU intensive steps, such as the R-only and C-only delay calculations implemented in the STAR-R system, to achieve fast and accurate parasitic RC results.